This book addresses "front end" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q and A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book.
With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL.
Summary: Very good Verilog and hardware design book
Rating: 4
This book tries to do three things: 1) introduce designers to some of the idiosynchrasies and pitfalls of the Verilog language, 2) teach some important basic digital design principles, and 3) go beyond pure functionality and help designers appreciate testability, verification, and emergent system performance issues. It does very well in all, I think. They do not mire themselves down in the detailed syntax or semantics of Verilog except in avoiding the aforementioned pitfalls. On the whole, t Read more...
